1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and, more specifically, to field shield isolation of cells within a semiconductor memory device array. The invention is also related to a manufacturing method thereof.
2. Description of the Prior Art
Recently, semiconductor memory devices are in great demand as information machines such as computers have come into wide use. Semiconductor memory devices having large memory capacitance capable of high speed operation are desired. Accordingly, the technology in association with the higher degree of integration, high speed responsiveness and higher reliability of the semiconductor memory devices has been developed.
DRAMs (Dynamic Random Access Memory) are the semiconductor memory devices capable of inputting and outputting data at random. Generally, a DRAM comprises a memory cell array which is a memory region storing a number of data, and peripheral circuits necessary for external input/output.
FIG. 5 is a block diagram showing a structure of a common DRAM. Referring to the figure, the DRAM 50 comprises a memory cell array 51 for storing data signals representing memory information; a row and column address buffer 52 for externally receiving an address signal to select a memory cell constituting a unit memory circuit; a row decoder 53 and a column decoder 54 for designating the memory cell by interpreting the address signal; a sense refresh amplifier 55 for amplifying the signal stored in the designated memory cell to read the same; a data in buffer 56 and a data out buffer 57 for inputting/outputting data, respectively; and a clock generator 58 for generating clock signals.
The memory cell array 51 occupying a large area on a semiconductor chip is constituted by an arrangement of a plurality of memory cells each storing a unit data. The improvement of the degree of integration of the memory cell array is essential in realizing higher degree of integration of the DRAM. There are mainly two methods for improving the degree of integration of the memory cell array. The first method is to miniaturize the structure of transistors and the like constituting the memory cell. The second method is to reduce area of an isolating region which insulates and isolates memory cells from each other. In the following, the latter method of reducing the element isolating region will be described.
A conventional structure for isolating elements in a memory cell array of a DRAM generally employs a thick oxide film selectively formed by LOCOS (Local Oxidation of Silicon) method. This is disclosed in, for example, Japanese Patent Laying Open No. 62-190869. In this method, a thick oxide film region is formed by the LOCOS method around a region in which an element is formed, whereby elements are insulated and isolated from each other. However, in the LOCOS method, an oxide film region called a bird's beak is formed, which extends from the periphery of the thick oxide film region to the region in which the element is formed. The bird's beak region reduces the area of the region in which the element is formed. In addition, the length of the bird's beak is constant irrespective of the reduction of the size of the entire element, so that the proportion of the area of the bird's beak to the area of the element forming region increases as the degree of integration of the structure becomes higher and higher. The bird's beak is one factor preventing higher degree of integration.
Meanwhile, FIG. 6 shows an example of the field shield isolating structure which insulates and isolates memory cells of the DRAM. Such structure is disclosed in, for example, Japanese Patent Laying-Open No. 62-10662. This figure shows a cross sectional structure of 2 bits of memory cells. The memory cell comprises one transfer gate transistor 2 and one capacitor 3, as in the above example. The field shield isolating structure is employed as the element isolating structure between adjacent memory cells. Namely, a shielding electrode layer 13 is formed on the surface of the semiconductor substrate 4 between the impurity diffused region 5a of one memory cell 1a and the impurity diffused region 5b of the other memory cell 1b with an oxide film 12 interposed therebetween. In this example, the shielding electrode 13 is connected integrally with the upper electrode 11 of the capacitor 3. By the application of a substrate potential or a lower potential to the shielding electrode 13, for example, the transistor structure constituted by the shielding electrode 13 and the impurity diffused regions 5a and 5b of the memory cells 1a and 1b is always kept at the off state. Thus the insulating isolation between the memory cells 1 a and 1b can be realized.
Now, in this example, the shielding electrode 13 and the upper electrode 11 of the capacitors 3 are connected together to be set at a common potential. Therefore, it is disadvantageous when the potential of the shielding electrode 13 should be set at a desired level without influencing the capacitors 3. The element isolating structure and the memory cell structure should preferably be formed independently to increase degree of freedom in the arrangement of the memory cell and in the manufacturing process to enable application to the DRAMs having various memory cell structure. (This will be described later).
Then, field shield isolating structure having an independent field shield electrode is described in, for example, Japanese Patent Publication No. 61-55258. FIG. 7 is a plan view of a memory cell of a DRAM employing the field shield isolating structure shown in this example, and FIG. 8 shows a cross sectional structure taken along the line VII--VII of FIG. 7. Memory cells of 2 bits are shown in these figures. The memory cell 1 is constituted by a transfer gate transistor 2 and a capacitor 3. The transfer gate transistor 2 is formed of two impurity regions 5 and 6 formed on a surface region of a semiconductor substrate 4 and a gate electrode 8 formed on the surface of the semiconductor substrate 4 with a thin insulating film 7 interposed therebetween. The capacitor 3 comprises a lower electrode 9 a portion of which connected to the impurity diffused region 6 of the transfer gate transistor 2, a dielectric layer 10 formed thereon, and an upper electrode 11 covering the upper surface thereof.
The element isolating structure of the DRAM of this example will be described in the following. A shielding electric layer 13 is formed on the surface of the semiconductor substrate 4 in the element isolating region with a gate oxide film 12 for shielding interposed therebetween. A pair of adjacent memory cells (only one is shown) sandwiching the shielding electrode layer 13 are arranged such that the impurity diffused region 6 of the memory cell 1 and the shielding electrode layer 13 constitute a transistor structure. By applying a potential of approximately the same level as the substrate to the shielding electrode layer 13, for example, the transistor structure becomes a normally-off transistor structure in which there will be no conduction between adjacent memory cells. Thus the insulating isolation between elements is realized.
Although the above described field shield isolating structure is employed for isolating elements in the X direction of FIG. 6, the isolating structure employing a thick oxide film provided by the LOCOS method is still used for isolating elements in the Y direction for isolating elements in the memory cell of this example. Therefore, as for the structure of the isolating region in the Y direction, there are still factors preventing higher degree of integration such as bird's beak.